{"id":23171,"date":"2021-03-03T04:24:22","date_gmt":"2021-03-03T04:24:22","guid":{"rendered":"https:\/\/rbsitsoftwaresolution.com\/blog\/linux-foundation-and-risc-v-international-launch-free-risc-v-training-classes.html"},"modified":"2021-03-03T04:24:22","modified_gmt":"2021-03-03T04:24:22","slug":"linux-foundation-and-risc-v-international-launch-free-risc-v-training-classes","status":"publish","type":"post","link":"https:\/\/www.rbsitsoftwaresolution.in\/blog\/linux-foundation-and-risc-v-international-launch-free-risc-v-training-classes.html","title":{"rendered":"Linux Foundation and RISC-V International launch free RISC-V training classes"},"content":{"rendered":"

RISC-V<\/a>, the emerging open-source instruction set processor architecture, is growing up. Sure, most of the attention has come from hardware hackers playing on RISC-V processors on development boards from companies such as\u00a0SiFive<\/a>. SparkFun<\/a>, and BeagleBoard<\/a>. There’s even a BBC Doctor Who-branded RISC-V mini-computer<\/a> for kids. But, according to RISC-V CTO Mark Himelstein, RISC-V processors have already found a home in data centers and Alibaba cloud servers. So, it’s high time for classes on how to use this new open-source hardware architecture.<\/p>\n

\n\t\tZDNet Recommends<\/span>
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\n The best Linux Foundation classes
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Want a good tech job? Then you need to know Linux and open-source software. One of the best ways to pick them up is via a Linux Foundation course.<\/p>\n

\n Read More<\/a>\n <\/p>\n

Thus, The Linux Foundation<\/a>, the non-profit organization enabling innovation with open source, and RISC-V International<\/a>, the non-profit corporation behind the RISC-V instruction set architecture (ISA), have released two new free online training courses to help you get started with the RISC-V ISA. The courses are available on edX.org<\/a>.<\/p>\n

With the recent rise of interest and deployment of RISC-V cores, systems-on-chips (SoCs), developer boards, and software and tools, there’s a real need to empower individuals to implement and use RISC-V. In order to help meet that demand, these free online courses are designed to significantly reduce the barrier to learning RISC-V skills.<\/p>\n

The first class, Introduction to RISC-V (LFD110x)<\/a>, guides you through the RISC-V ecosystem, the RISC-V specifications, how to curate and develop RISC-V specifications, and the technical aspects of working with RISC-V both as a developer and end-user. The course provides you with the knowledge you’ll need to engage in the RISC-V community; contribute to the ISA specifications; and develop a wide range of RISC-V software and hardware projects. Jeffrey “Jefro” Osier-Mixon, program manager for RISC-V International, and Stephano Cetola, technical program manager for RISC-V International, developed this course.\u00a0<\/p>\n

The second course, Building a RISC-V CPU Core (LFD111x)<\/a>, focuses on digital logic design and basic central processing unit (CPU) microarchitecture. In it, you’ll learn to use the Makerchip<\/a> online integrated development environment (IDE). You’ll implement technologies ranging from logic gates to a simple and complete RISC-V CPU core. The class will allow participants to familiarize themselves with a variety of emerging technologies supporting an open-source hardware ecosystem, including RISC-V transaction-level verilog<\/a>. Steve Hoover, founder of Redwood EDA<\/a>, developed this class.
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Calista Redmond, RISC-V International’s CEO, said in a statement: “RISC-V International is committed to providing opportunities for people to gain a deeper understanding of the RISC-V ISA and expand their skills. These courses will allow everyone to build deeper technical insight, learn more about the benefits of open collaboration, and engage with RISC-V for design freedom.”
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You can enroll now in both Introduction to RISC-V and Building a RISC-V CPU Core. Auditing each course through edX is free for seven weeks. For $149 per class, you can opt for a paid verified certificate of completion. This also gives you access to the course for a full year and additional assessments and content to deepen their learning experience.\u00a0<\/p>\n

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